1. Field of the Invention
The present invention relates to a microcomputer with a built-in flash memory.
2. Description of Related Art
Recently, flash memories have rapidly come onto the market. This is because, unlike EPROM (Erasable Programmable Read-Only Memory) requiring ultraviolet light for erasing, erasure as well as writing of data can be easily achieved electrically with flash memories, and hence the once written data can be easily updated.
The microcomputer with a flash memory in place of a mask ROM or EPROM has also been rapidly extending its markets. The flash memories embedded in the microcomputer are used for storing programs or data.
The flash memory installed in the microcomputer can be programmed (written) and erased with a flash memory writer included in a single chip with the flash memory. The flash memory writer, however, cannot write/erase (usually called "rewrite") the flash memory after the microcomputer with the built-in flash memory has been mounted on a circuit board. This is because the flash memory writer carries out the write/erasure of the flash memory while mounting the microcomputer package including the flash memory, and hence cannot write/erase the microcomputer with the built-in flash memory mounted on circuit board.
To solve this problem, a microcomputer with a built-in flash memory which has a CPU rewrite function has been proposed so that the write/erasure of the flash memory in the microcomputer with a built-in flash memory can be achieved even after the microcomputer package has been mounted on the circuit board by using a CPU included therein.
FIG. 7 is a block diagram showing an example of a conventional microcomputer with a built-in flash memory having a CPU rewrite function. In this figure, the reference numeral 1 designates a microcomputer, 2 designates a CPU, 3 designate a flash memory embedded in the microcomputer 1, 4 designates a flash control circuit for carrying out write/erasure of the flash memory 3 by executing a write command or an erasure command issued by the CPU 2, 5 designates a data bus, 6 designates an input/output port as an interface with external devices, 7 designates a clock generator, 8 designates a monitor timer, 9 designates an interrupt controller, 10 designates peripheral devices of the microcomputer 1, 20 designates an external data bus, 22 designates a personal computer (PC) for outputting data to be written in the flash memory 3, 21 designates an interface (I/F) for connecting the external data bus 20 with the personal computer 22, and 23 designates an oscillator.
FIG. 8 is a block diagram showing the details of the flash control circuit 4. In this figure, the reference numeral 31 designates a flash write/erasure executer for carrying out write/erasure of the flash memory 3, 32 designates a flash control register for exchanging with the CPU 2 control data for controlling the flash write/erasure executer 31, 32a designates a busy bit which is provided in the flash control register 32 and is referred to as a "CPU rewrite mode designating bit", and 33 designates a flash command register in which the CPU 2 writes a write command or erasure command.
Next, the operation will be described.
The clock generator 7 generates a clock signal 71 for the CPU 2, a clock signal 72 for the monitor timer 8 and a clock signal 73 for the peripheral devices 10 using a clock signal with a fundamental frequency, which is generated by the oscillator 23 and supplied via ports 17 and 18, and supplies the clock signals to the corresponding devices.
The monitor timer 8 receives the clock signal 72, and counts it. In the case where the monitor timer 8 is a count-up type, it outputs an overflow signal 81 to the interrupt controller 9 every time the overflow occurs. On the other hand, when the monitor timer 8 is a count-down type, it outputs an underflow signal to the interrupt controller 9 each time the underflow occurs. For simplicity, it is assumed that the monitor timer 8 is a count-up type in the following description.
Receiving the overflow signal 81 from the monitor timer 8, the interrupt controller 9 generates a monitor timer interrupt request signal 91 to the CPU 2.
The monitor timer 8 is originally provided for detecting the CPU 2 running out of control, in which case the interrupt controller 9 causes the monitor timer interrupt request signal 91 after a predetermined time period has elapsed, and the CPU 2 recognizes by itself that it is running out of control by detecting the monitor timer interrupt request signal 91. Thus, the CPU 2 returns to normal operation by executing interrupt handling associated with the monitor timer interrupt request signal 91.
To achieve the original role of the monitor timer 8, it is preferable that no unnecessary overflow occur. Thus, the CPU 2 resets the monitor timer 8 at intervals within a predetermined time period.
The data writing operation to the flash memory 3 by the CPU 2 will now be described.
The personal computer (PC) 22 suitably supplies the interface (I/F) circuit 21 with data to be written, and the program for writing data to the flash memory 3 using the CPU 2 has been stored in the flash memory 3 itself so that the CPU 2 writes the data to the flash memory 3 by executing the program. In this case, the flash memory 3 includes separate areas for writing data and for storing the program. The area for storing the program can be set to a write disabled state, and the program can be read therefrom even when data is being written to the area for writing data.
Although there is a system which stores the program writing data to the flash memory 3 in a RAM installed in the CPU 2, it is not explained here.
The CPU 2 sets a flag (writes "1", for example) in the CPU rewrite mode, designating bit 32a in the flash control register 32 provided in the flash control circuit 4 as shown in FIG. 8. As a result, the flash control register 32 outputs the CPU rewrite mode designating signal 41 to the flash write/erasure executer 31. Receiving the CPU rewrite mode designating signal 41, the flash write/erasure executer 31 enters the waiting state so that it can execute a command written in the flash command register 33.
When the CPU 2 writes a write command to the flash command register 33 during the waiting state, the flash write/erasure executer 31 decodes the write command, and starts the sequence for writing data to the flash memory 3.
First, the CPU 2 reads the data to be written from the personal computer (PC) 22 via the interface (IF) circuit 21, and transfers the data to the flash memory 3 through the data bus 5. Then, the flash write/erasure executer 31 writes the transferred data into the flash memory 3 in accordance with a predetermined sequence. Although not shown in the drawings, the flash write/erasure executer 31 includes a ring oscillator, a clock generator and a sequencer for generating a clock signal so that procedures for writing data are carried out at respective time intervals by counting the clock signal.
Writing by the flash write/erasure executer 31 is carried out independently of the operation of the CPU 2. This means that the CPU 2 is set free after writing the write command into the flash command register 33, and this makes it possible for the CPU 2 to use its CPU time for other subsequent processing.
The flash write/erasure executer 31 outputs a write/erasure busy signal 42 during the writing The write/erasure busy signal 42 sets to enabled state ("1", for example) the CPU rewrite mode designating bit 32a in the flash control register 32. The CPU 2 can read the CPU rewrite mode designating bit 32a via the data bus 5. The CPU 2 continues to read it during the write processing (called polling), and awaits the CPU rewrite mode designating bit 32a to be disabled (to become "0" in this case) by the completion of the writing.
Confirming that the CPU rewrite mode designating bit 32a is disabled, the CPU 2 verifies whether the data has been written correctly in the flash memory 3. There are two methods for the verification: One verifies the data by directly reading the written data from the flash memory 3, and the other writes a write compare command in the flash command register 33.
After confirming the validity of the data written into the flash memory 3 as a result of the verification, the CPU 2 writes the write command in the flash command register 33 to write the next data.
Next, the erasure of the flash memory 3 by the CPU 2 will be described.
First, the CPU 2 sets a flag in the CPU rewrite mode designating bit 32a in the flash control register 32 provided in the flash control circuit 4, and then writes an erasure command into the flash command register 33. In this case, the flash memory 3 includes separately an area to be erased and an area for storing a program for erasure. The latter area can be set to erasure disabled state, and the program for erasure can be read therefrom even when the former area is being erased.
The flash write/erasure executer 31 decodes the erasure command written into the flash command register 33 and carries out the erasure of the flash memory 3 in accordance with a predetermined sequence.
The flash write/erasure executer 31 outputs the write/erasure busy signal 42 while executing erasing. The write/erasure busy signal 42 sets to enabled state ("1", for example) the CPU rewrite mode designating bit 32a in the flash control register 32. As mentioned above, the CPU 2 can read the CPU rewrite mode designating bit 32a through the data bus 5. Thus, the CPU 2 continues to carry out polling of the CPU rewrite mode designating bit 32a during the erasure interval, and awaits the CPU rewrite mode designating bit 32a to be disabled (to be set to "0" in this case) by the completion of the erasure.
It should be noticed here that the write time and erasure time of the flash memory 3 are much longer than the cycle time of the CPU 2, ranging from 100 to 1000 times the cycle time. This will result in the overflow of the monitor timer 8, causing unnecessary monitor timer interrupts. To prevent this, the CPU 2 must reset the monitor timer 8 within a certain time interval.
Since the monitor timer 8 is originally provided for detecting the CPU 2 running out of control, it is not preferable for the unnecessary overflow to occur. Since the writing or erasure of the flash memory 3, however, causes overflow of the monitor timer 8, it must be reset more frequently than usual, which results in overloading of software.
In the foregoing example, the CPU 2 detects the completion of the writing or erasure of the flash memory 3 by continuously polling the CPU rewrite mode designating bit 32a during the writing or erasure. This method, however, does not enable the CPU 2 to stand by. That is, the CPU 2 cannot handle other processes because most of the CPU time is used for the polling.
It is necessary to remove the polling to enable the CPU 2 to stand by. To achieve this, the flash write/erasure executer 31 can request the interrupt controller 9 to generate an interrupt request when the writing or erasure of the flash memory 3 has been completed, so that the completion is indicated to the CPU 2 by means of interrupt.
In the foregoing example, it is assumed that the flash memory 3 includes separate areas for write/erasure and the area for storing the program for write/erasure, and the write/erasure program can be read out of the latter area even during the writing/erasing. Some microcomputers with a built-in flash memory, however, have a flash memory which inhibits reading the area for storing the writing/erasing program during writing/erasing, even though their flash memories are separated into the area for the writing/erasing and the area for storing the writing/erasing program so that an area can be established in which the data cannot be written. Since the writing/erasing program cannot be read during the writing/erasing in this case, it is necessary for such microcomputers to transfer the writing/erasing program to a RAM before carrying out the writing/erasing so that the writing/erasing of the flash memory 3 is performed by the writing/erasing program stored in the RAM.
In summary, the conventional microcomputers with a built-in flash memory with the foregoing configurations have the following problems.
(1) The CPU must continue polling for detecting the completion of writing or erasing or erasure throughout writing or erasing or erasure of the flash memory, and hence the polling results in the overload of the software. PA0 (2) If the method using the interrupt to inform the CPU of the completion of the writing or erasure is employed instead of the polling, CPU time is consumed to execute the interrupt handler. PA0 (3) It is necessary for the CPU to frequently reset the monitor timer at predetermined intervals to prevent the overflow of the monitor timer due to the writing or erasure of the flash memory. This requires an instruction for resetting the monitor timer to be inserted at various places of the program, which results in the overload in a control software. In addition, this requires considerable time for checking whether the reset instruction of the monitor timer is suitably placed, which will retard the development of the software. PA0 (4) It is necessary for the microcomputer with a built-in flash memory, in which reading from the program area is inhibited during writing/erasing of the flash memory, to transfer the writing/erasing program to the RAM so that writing/erasing is executed according to the program written in the RAM. This results in an increase of the load on the software. In addition, since the capacity of the RAM (usually a few percent of the capacity of the ROM) imposes restrictions on the program, the writing/erasing program with a scale sufficient for implementing detailed algorithm cannot be installed.